Technical / research

Strategic Elements announces has signed an agreement with the University of New South Wales (UNSW) to further optimize the company's Nanocube Memory Ink flexible/transparent RRAM technology. UNSW and SER will also develop demonstrator applications for the new technology.

UNSW will begin the research by assessing potential demonstrator applications in areas such as multi-functional capacitive sensors that can detect the type and strength of external stimuli including curvature, pressure, strain, and touch with clear distinction. It will also look into developing memory arrays that will fulfill the growing requirement for local digital data storage on flexible sensors, tags, wearables and high value consumer packaging.

Israel-based SiOx RRAM developer Weebit Nano demonstrated in November 2017 a 40nm working ReRAM memory cell. The company has now announced that it has successfully scaled up the single memory cell into a 4Kb array.

Weebit Nano says that an analysis of the 4Kb wafers showed no degradation due to scaling. The company is now confident in its goal of a working 40nm 1Mb array by mid-2018.

Earlier this year, Weebit Nano announced that it aims to produce 40nm working SiOx RRAM cell samples by the end of 2017, and the company today announced that it achieved that milestone - one month ahead of schedule.

Weebit further reports that measurements performed on the 40nm memory cells on various wafers verified the ability of Weebit Nano SiOx ReRAM cells to maintain its memory behaviour in accordance with previous experiments performed on 300nm cells.

Australia-based RRAM developer 4DS Memory announced that it has signed an agreement with Belgium-based imec to develop a transferable manufacturing process for its technology. As part of the agreement the two parties will demonstrate the process with a 1Mbit test chip.

In October 2016 4DS raised $3 million USD to fund its ongoing ReRAM development activities. In October 2016 4DS also announced the fabrication of a working 40nm RRAM memory cell in collaboration with HGST, a subsidiary of Western Digital.

Weebit Nano announced that it has managed to produce a 4Kb array on 300 nm cells, with 100% yield on selected arrays. Weebit says that this result validates its technology and that this demonstration was the final significant step towards the next goal for the company - a 40nm RRAM Silicon Oxide working cell by the end of 2017.

Preliminary speed tests of Weebit's technology showed that write speeds could be 100 to 1000 times faster than traditional 3D Flash technology while using significantly lower energy.

Researhcers at Stanford and MIT developed a new 3D chip fabrication method that combines a CNT-based processor with RRAM memory cells. This technology can be used to create 3D chip architectures in a way that is not possible with silicon-based chips.

Both CNT-based logic and RRAM memory components can be deposited at relatively low temperatures (around 200 degrees Celsius) as opposed to silicon which requires 1,000 degrees to deposit. This means that you can place one layer on top of the other without damaging either layers.

Researchers from Soochow University in China developed a 2D RRAM device structure based on sheets of graphene and hexagonal boron nitride (hBN). The device uses a Graphene/hBN/Graphene structure and it features excellent overall fitting results.

This is still just a theoretical model, but it may prove to be the basis of high performance RRAM devices.

Researchers from the Munich University of Applied Sciences in Germany managed to produce RRAM (CBRAM) devices using a standard inkjet printer (FujiFilm Dimatix DMP 2831) without any additional processing steps such as electroplating or lithography. The researchers say that the memory devices have a performance comparable to regular RRAM devices created in a clean-room process.

To create these memory cells, the researchers used three different inks: silver nanoparticles, spin-on-glass (liquid glass) and PEDOT:PSS. The silver created the conductive layer, the spin-on-glass was the insulating layer and the PEDOT:PSS was also used to create conductive layers. The memory device was printed on a cheap and flexible plastic foil.

Researchers from Soochow University in China in collaboration with researchers form Harvard, Stanford and MIT developed RRAM memory devices using multilayer hexagonal boron nitride (h-BN) as dielectric. The devices show promising performance - while being based on a 2D material, which may pave the way towards extremely thin and efficient memory devices.

2D materials (such as h-BN and others) are interesting to many researchers, and the field is experiencing a boom following the "discovery" of graphene in 2004.

Researchers from the Guizhou Institute of Technology in China produced RRAM devices using finely ground used egg shells. These devices were not very durable - they only lasted about 100 write cycles...

To create the devices, the researchers ground the egg shells until they got a 'nanoscale' powder. They then dried it and dissolved it in a solution. The solution was than used to coat a substrate to form the electrolyte part of the RRAM device.