Researchers from CEA-Leti, Spintec and C2N (Université Paris-Saclay) have developed a hybrid nanoelectronic Ising machine that combines hafnium-oxide RRAM with stochastic magnetic tunnel junctions (SMTJs). Such a machine searches for the lowest-energy state of a network of interacting binary variables, which makes it a good fit for hard combinatorial optimization problems such as vehicle routing, power-grid balancing and chip layout.

In the new system, an RRAM crossbar array encodes the graph of the problem, while the SMTJs, whose magnetization flips randomly under ordinary thermal noise, act as probabilistic bits. The two are connected in a single loop, so the system moves toward better solutions without a digital controller managing every update. The researchers also found that tuning the read voltage across the RRAM array gradually suppresses the randomness of the SMTJs as the search progresses, which provides the annealing behavior intrinsically, without extra circuitry.

Australia-based RRAM developer dorsaVi announced that it has begun to test its first RRAM structure, to measure the energy required to update memory states. The company says that this work is intended to establish an initial energy-performance benchmark for dorsaVi’s low-power hardware pathway before more comprehensive testing with its RRAM Validation Chip.

dorsaVi says that it sees physical AI, including advanced robotics, autonomous systems and adaptive wearables, as a potential application area where local memory and processing could reduce the need to send all raw sensor data to a distant processor.

Researchers from Taiwan's National Cheng Kung University developed RRAM memory based on lead-free Na0.5K0.5NbO₃/HfO perovskite materials. The researchers fabricated a device using low-temperature sputtering, and report high performance and excellent process compatibility. 

The researchers say that the new device exhibits forming-free switching, low operating voltages (−1 V/1.5 V), a high ON/OFF ratio of ∼200, and endurance exceeding 105 cycles.

4DS Memory announced that it plans to acquire a new an edge-AI and autonomous systems software developer called Jenesys Pty Ltd. The company seeks to raise $5 million AUD to fund this acquisition, which also includes performance rights. 

Jenesys Pty was established in November 2025, and it seeks to build coordination software for drone swarms. that need to keep working when GPS and communications drop out. 4DS will pay A$5 million in shares at A$0.01 plus performance rights tied to revenue milestones.

4DS Memory announced its financial results for Q2 2026, with a 11% increase in revenue to $243,000 USD, and a net loss of $1.14 million USD - down 85% from last year.

The company says that the improved earnings reflect the company's improved cost control and its new strategic shift toward commercialization of the 60nm RRAM platform with a focus on India's mature-node semiconductor market.

Australia-based RRAM developer dorsaVi announced that it has commenced physical manufacturing of its first RRAM-CMOS validation chip. The company's manufacturing data package has passed foundry intake, the wafer lot has been committed to fabrication, and processing is now underway on the front-end CMOS base.

The chip began its tape-out process in July 2026, and the current run will produce the transistor and circuit-level structures needed to support the RRAM memory array, the peripheral circuits and various evaluation features - before the RRAM-specific layers are added. Once the CMOS base is complete, the wafers will move on to partner-led back-end-of-line processing and RRAM stack integration, followed by electrical testing and characterisation.

Researchers from Peking University in Beijing, China, working with the Beijing Advanced Innovation Center for Integrated Circuits, have proposed a protection framework for RRAM-based deep neural network (DNN) accelerators. In this framework, the researchers split accelerator security into two distinct levels. The framework, called OmniGuard, achieves a 1.33x to 4.38x speedup and 1.26x to 2.65x power savings, with a reported 5% energy overhead and 3% area overhead.

RRAM-based computing-in-memory (CIM) accelerators have become one of the mainstream options for running neural network inference on edge devices, as performing the multiply-accumulate operation inside the memory array itself avoids the data movement that dominates the energy budget of conventional von Neumann designs. But edge hardware sits in the field, physically accessible to whoever holds it, and the trained model weights programmed into the RRAM array are usually the most valuable asset on the chip. The researchers note that these security vulnerabilities are a real obstacle to deploying RRAM-based accelerators commercially.

Researchers from the College of Electronic and Optical Engineering at Nanjing University of Posts and Telecommunications (NJUPT) in Nanjing, China, have designed, fabricated and measured a single-pole single-throw (SPST) RF switch built on an RRAM process. The switch operates across the DC-Ku band with a measured insertion loss below 1 dB, and it holds its state without any standing bias.

RF switches sit in the front-end of nearly every wireless system, routing signals between transmit and receive paths. The standard options used today, field-effect transistors, PIN diodes and RF MEMS, all share a drawback: they need a continuous bias voltage or drive current to stay in either the ON or the OFF state. Over long operating periods that translates into meaningful static power draw and thermal management headaches, which is exactly the wrong trade-off for battery-powered IoT nodes and wearables.

Researchers at China's Tsinghua University, together with InnoMem Technologies, have developed a 16Mb embedded RRAM device with a hybrid array structure, built on a 28 nm process, that is highly suited for automotive OTA update applications.

The researchers say that the new 1T1R/2T2R hybrid array structure design enhances the reliability and system compatibility. The researcher used several technologies to increase performance - a load balancing approach to address the IR-drop issue and improve cell uniformity, and a hierarchical column selection strategy to suppress the leakage current in the write path, optimizing write operations at high temperature.

RRAM developer Weebit Nano announced that it has successfully raised $87 million AUD (about $60 million USD) through placements with institutional investors and a separate offering in Israel.

The company will use the funds to support both technical advancements and commercial expansion.