RRAM-Info: the RRAM experts

Researhcers at MIT developed a new 3D chip fabrication method that combines a CNT-based processor with RRAM memory cells. This technology can be used to create 3D chip architectures in a way that is not possible with silicon-based chips.

Both CNT-based logic and RRAM memory components can be deposited at relatively low temperatures (around 200 degrees Celsius) as opposed to silicon which requires 1,000 degrees to deposit. This means that you can place one layer on top of the other without damaging either layers.

Researchers at Moscow's Institute of Physics and Technology (MIPT) developed a method of depositing the functional layers of an RRAM memory cell using high quality ALD coating. The researchers report that ALD enables a controllable growth of oxygen deficient oxides.

The MIPT researchers used production-proven ALD equipment made by Picosun. The researchers now want to see whether the ALD process can be scaled to an industrial-scale production process.

According to reports, Taiwan Semiconductor Manufacturing Company (TSMC) is aiming to start producing embedded RRAM chips in 2019 using a 22 nm process. This will be initial "risk production" to gauge market reception.

TSMC also aims to start embedded MRAM chip production in 2018.

Researchers from Soochow University in China developed a 2D RRAM device structure based on sheets of graphene and hexagonal boron nitride (hBN). The device uses a Graphene/hBN/Graphene structure and it features excellent overall fitting results.

This is still just a theoretical model, but it may prove to be the basis of high performance RRAM devices.

Researchers from the Munich University of Applied Sciences in Germany managed to produce RRAM (CBRAM) devices using a standard inkjet printer (FujiFilm Dimatix DMP 2831) without any additional processing steps such as electroplating or lithography. The researchers say that the memory devices have a performance comparable to regular RRAM devices created in a clean-room process.

To create these memory cells, the researchers used three different inks: silver nanoparticles, spin-on-glass (liquid glass) and PEDOT:PSS. The silver created the conductive layer, the spin-on-glass was the insulating layer and the PEDOT:PSS was also used to create conductive layers. The memory device was printed on a cheap and flexible plastic foil.

Weebit Nano announced that electrical tests conducted on its SiOx RRAM at the Leti institute in France has been succesful. Leti performed extensive testing on critical memory parameters such as programming and erase voltage.

Weebit further says that it is now able to move forward with its plans to scale down the RRAM technology to 40nm.