In the device, a graphene strip was placed on top of a flake of STO (strontium titanium oxide perovskite). The graphene strip addition enabled the usage of the STO material at higher temperatures than before. This research creates new insights into the adoption of STO materials in memristor devices.
Researchers from Korea's Pohang University of Science & Technology (POSTECH) has designed a halide perovskite material for RRAM memory devices. The perovskite material offers low-operating voltage and high-performance resistive switching memory.
The researcher say they have succeeded in designing an optimal halide perovskite material (CsPb2Br5) that can be applied to a ReRAM device by applying first-principles calculation based on quantum mechanics.
Singapore's Nanyang Technological University (NTU Singapore) and GlobalFoundries announced a partnership to jointly research next-generation RRAM memories. The two partners will invest $88 million USD with an aim to demonstrate RRAM memory devices produced on 12-inch wafers.
NTU and GF-Singapore are already collaborating on spintronics - the study of electron spin and its applications, including MRAM memory (NTU and GF are founding members of the Singapore Spintronics Consortium. In this new ReRAM project, 16 researchers will work together to research areas such as circuit design for next-generation smart devices and chip packaging for advanced IoT applications.
Israel-based SiOx RRAM developer Weebit Nano has signed an agreement to collaborate with the Technion Institute in Israel. Weebit will work together with a team of researchers to examine the possible use of ReRAM devices in processing-in-memory that could speed up processing, memory transfer rate and memory bandwidth and decrease processing latency – while using less power.
Weebit and the Technion will also perform characterisation and implementation of logic operations using Weebit’s RRAM test chips, demonstrating basic logic operations on a RRAM array
Israel-based SiOx RRAM developer Weebit Nano launched a joint Neuromorphic ReRAM project with
Politecnico di Milano (Polimi). Weebit Nano's team will collaborate with researchers from the Poltecnico to test, characterize and implement its developed algorithms using Weebit’s ReRAM chip. The goal of the project is to demonstrate the capability of ReRAM-based hardware in neuromorphic and artificial intelligence applications.
This is the second Neuromorphic RRAM project that Weebit launches - only recently in November 2018 it announced that it will partner in a similar project with the Non-Volatile Memory Research Group of the Indian Institute of Technology Delhi (IITD).
Strategic Elements announces has signed an agreement with the University of New South Wales (UNSW) to further optimize the company's Nanocube Memory Ink flexible/transparent RRAM technology. UNSW and SER will also develop demonstrator applications for the new technology.
UNSW will begin the research by assessing potential demonstrator applications in areas such as multi-functional capacitive sensors that can detect the type and strength of external stimuli including curvature, pressure, strain, and touch with clear distinction. It will also look into developing memory arrays that will fulfill the growing requirement for local digital data storage on flexible sensors, tags, wearables and high value consumer packaging.
Israel-based SiOx RRAM developer Weebit Nano demonstrated in November 2017 a 40nm working ReRAM memory cell. The company has now announced that it has successfully scaled up the single memory cell into a 4Kb array.
Weebit Nano says that an analysis of the 4Kb wafers showed no degradation due to scaling. The company is now confident in its goal of a working 40nm 1Mb array by mid-2018.
Earlier this year, Weebit Nano announced that it aims to produce 40nm working SiOx RRAM cell samples by the end of 2017, and the company today announced that it achieved that milestone - one month ahead of schedule.
Weebit further reports that measurements performed on the 40nm memory cells on various wafers verified the ability of Weebit Nano SiOx ReRAM cells to maintain its memory behaviour in accordance with previous experiments performed on 300nm cells.
Australia-based RRAM developer 4DS Memory announced that it has signed an agreement with Belgium-based imec to develop a transferable manufacturing process for its technology. As part of the agreement the two parties will demonstrate the process with a 1Mbit test chip.
In October 2016 4DS raised $3 million USD to fund its ongoing ReRAM development activities. In October 2016 4DS also announced the fabrication of a working 40nm RRAM memory cell in collaboration with HGST, a subsidiary of Western Digital.
Weebit Nano announced that it has managed to produce a 4Kb array on 300 nm cells, with 100% yield on selected arrays. Weebit says that this result validates its technology and that this demonstration was the final significant step towards the next goal for the company - a 40nm RRAM Silicon Oxide working cell by the end of 2017.
Preliminary speed tests of Weebit's technology showed that write speeds could be 100 to 1000 times faster than traditional 3D Flash technology while using significantly lower energy.