Crossbar

CrossBar announced that its RRAM memory technology is inherently resistant to physical hacking targeting sensitive information and data stored in memory. This could lead to new applications where resistance to reverse engineering and physical attacks are essential requirements of the system.

Cross bar says that its filamentary-based ReRAM has been demonstrated to provide unique levels of security, including strong resistance to attempts to read the memory through invasive physical hacking. Cross further says that MicroNet Solutions (MSI) performed extensive delayering and inspection of CrossBar's ReRAM memory silicon through imaging techniques in an attempt to determine its stored content. After significant evaluation using sophisticated techniques such as measuring electron beam induced current and passive voltage contrast imaging, MSI was unsuccessful in determining the contents of the memory array.

CrossBar says that its partners are now starting to use its RRAM memory technology for few-time programmable (FTP) and one-time-programmable (OTP) NVM applications. This is in addition to CrossBar's "traditional" MTP non-volatile memory and PUF security applications.

CrossBar says that this new applications demand can be met with its current technology, but the company also offers to optimize its RRAM for FTP and OTP applications, which will significantly increase memory density and reduce the cost.

RRAM developer CrossBar announced (in July 2021) a new application of its RRAM technology for use as a physical unclonable function (PUF) in order to generate cryptographic keys in secure computing applications.

CrossBar's RRAM has been historically utilized as non-volatile semiconductor memory, but it is now being introduced for use in hardware security. The company says its solution can enable a more secure and cost-effective class of devices and systems.

RRAM developer Crossbar announced a new SPI-based AI accelerator chip, which it calls XPU. The chip targets a specific lookup phase during AI calculations and contains an RRAM memory device and a programmable coparator.

RRAM's low power and non-volatility nature fits this application and according to crossbar can achieve a 30X speed improvement over an ARM+DDR4 combination, while drawing 500X less power (the advantages of the XPU chip are increased with object length).

A new AI consortium was announced that aims to deliver a vastly accelerated, power-saving AI platform and standard that enables new AI-rich capability for edge computing, gateways, cloud and data centers. The idea is to combine advanced acceleration hardware, resistive memory (RRAM) and optimized neural networks to create "ready-made, power-efficient solutions with unsupervised learning and event recognition capability".

The SCAiLE (SCalable AI for Learning at the Edge) consortium is already working with Japanese authorities to review opportunities for the 2020 Olympics, including video-based event detection and response capability. The consortium members include RRAM developer Crossbar and AI accelerator startup Gyrfalcon Technology, which recently announced the commercial availability of its LightSpeeur 2802M AI ASIC that include TSMC's eMRAM memory.

Crossbar's VP of Business Development, Sylvain Dubois, demonstrates how the company's ReRAM memory can be used for artificial intelligence edge computing acceleration.

In the demonstration, the classification of license plates or face recognition is performed in only one iteration showing energy-efficient massive parallelism at deterministic performance.

Crossbar announced that Microsemi, the largest US military and aerospace semiconductor supplier, has signed a licensing agreement which will bring Crossbar's RRAM technology to Microsemi's products.

As part of the agreement, Microsemi and Crossbar will collaborate in the research, development and application of Crossbar’s proprietary ReRAM technology in next generation products from Microsemi.

Crossbar announced a partnership with Mobiveil, a supplier of silicon IP, platforms and IP-enabled design services to apply Mobiveil complete PCIe to NVMe set of solid state drive (SSD) IP to support Crossbar's RRAM IP blocks.

Mobiveil and Cross will work together on a new RRAM-based design from Mobiveil’s complete PCIe-to-NVMe set of SSD IP with Crossbar’s RRAM enabling six-million 512B IOPS below 10us latency. Crossbar says that the performance gain will enable RRAM-based SSDs to significantly speed up access to frequently requested information in large data centers.

In March 2016 Crossbar announced its strategic partnership with Semiconductor Manufacturing International Corporation (SMIC) to co-develop and produce RRAM technologies. In January 2017 Crossbar announced that it started sampling RRAM chips.

In an interesting interview with Electronic Design, Crossbar's Vice President of Strategic Marketing & Business Development, Sylvain Dubois, discloses that Crossbar has started to ramp up production, and has signed a dozen agreements to license its technology to MCU/SoC companies. Crossbar's current developments are targeting embedded ReRAM IPs integrated in MCUs/SoCs for IoT, consumer electronics, artificial intelligence, and industrial applications.

In March 2016 Crossbar announced its strategic partnership with Semiconductor Manufacturing International Corporation (SMIC) to co-develop and produce RRAM technologies. Crossbar now says it started to sample embedded RRAM chips from SMIC.

SMIC, China's largest semiconductor foundry, is using a 40nm process, and Crossbar says that it plans for a 28nm process - and even 10nm or lower down the road. The chip design uses non-conductive amorphous silicon (a-SI) technology. Crossbar's chips can either use a 1T1R architecture (1 transistor per RRAM, which offers the lowest latency and so useful for embedded memory and caching) or 1TnR (which uses up to 2,000 cells per transistor using a crossbar scheme - which makes for higher density chips useful for storage).