Weebit Nano announced that electrical tests conducted on its SiOx RRAM at the Leti institute in France has been succesful. Leti performed extensive testing on critical memory parameters such as programming and erase voltage.
Weebit further says that it is now able to move forward with its plans to scale down the RRAM technology to 40nm.
Researchers from Soochow University in China in collaboration with researchers form Harvard, Stanford and MIT developed RRAM memory devices using multilayer hexagonal boron nitride (h-BN) as dielectric. The devices show promising performance - while being based on a 2D material, which may pave the way towards extremely thin and efficient memory devices.
2D materials (such as h-BN and others) are interesting to many researchers, and the field is experiencing a boom following the "discovery" of graphene in 2004.
Rambus announced that it signed a broad patent license agreement with western digital. The agreement covers the use of several memory technologies - including memory architectures, high speed interfaces, security technologies and ReRAM.
Rambus did not provide any more details, but the agreement will last until 2021 with an option for an additional 5-year extension.
Panasonic announced a new partnership with Taiwan-based United Microelectronics Corp (UMC) to co-develop and produce RRAM devices. The two companies aim to use a 40nm process to produce RRAM chips that consume one-seventh the power of today's NAND flash memory.
Panasonic will be in charge of designing the chips, and the two companies will co-develop the microfabrication technologies. Actual production will be done at UMC. The two companies plan to start shipping samples in 2018 and mass produce RRAM chips by 2019. The first RRAM devices will be embedded in microcontrollers.
In March 2016 Crossbar announced its strategic partnership with Semiconductor Manufacturing International Corporation (SMIC) to co-develop and produce RRAM technologies. Crossbar now says it started to sample embedded RRAM chips from SMIC.
SMIC, China's largest semiconductor foundry, is using a 40nm process, and Crossbar says that it plans for a 28nm process - and even 10nm or lower down the road. The chip design uses non-conductive amorphous silicon (a-SI) technology. Crossbar's chips can either use a 1T1R architecture (1 transistor per RRAM, which offers the lowest latency and so useful for embedded memory and caching) or 1TnR (which uses up to 2,000 cells per transistor using a crossbar scheme - which makes for higher density chips useful for storage).
Researchers from the Guizhou Institute of Technology in China produced RRAM devices using finely ground used egg shells. These devices were not very durable - they only lasted about 100 write cycles...
To create the devices, the researchers ground the egg shells until they got a 'nanoscale' powder. They then dried it and dissolved it in a solution. The solution was than used to coat a substrate to form the electrolyte part of the RRAM device.
A team of international researchers, from China (Nanyang Technological University), Singapore (NTU) and Germany (RWTH Aachen University and Forschungszentrum Juelich) developed a technique to turn RRAM chips into logic processors.
The researchers say that these kind of processors eliminate the need to transfer data between memory storage and the computational unit (as it is now the same unit) - and so these processors could be at least two times faster than current processors. The new processors will also be smaller than current designs.
