Researchers from Leti presented a new paper that clarified for the first time the correlation between endurance, window margin and retention of RRAM. The researchers advice ways module these three key properties, in different RRAM types.

Each RRAM type and base material has a different "sweet spot" that offers the best performance in all three categories. Using modelling the researchers were able to address various non-volatile memory applications, targeting high speed, high endurance or high stability.

US-based RRAM developer 4DS Memory announced that it has measured the endurance yield of more than 1,000 cells of five different cell sizes on two different wafers, and more than 97% of the memory cells tested achieved the required endurance goal, significantly exceeding the target of 90% endurance yield.

4DS recently announced the fabrication of a working 40nm RRAM memory cell in collaboration with HGST, a subsidiary of Western Digital. The company also successfully completed a placement of $3 million USD.

Researchers from Stanford University are studying filament RRAM technologies to discover the fundamental behavior of these memory cells. The research team built a tool to measure the basic forces that make RRAM chips work - especially the heat requirements for RRAM switching.

Using micro thermal stage (MTS) devices, RRAM chips were studied under a wide range of temperatures, to try and find the exact temperature in which RRAM switching occurs. It was discovered that operating at 80 to 260 F is more efficient than the higher temperatures people thought were more efficient.

Researchers at the Chinese Academy of Sciences developed a new cation-based RRAM device in which a single layer graphene was used as an ion barrier. Experiments indicate that this device is more reliable than previous RRAM designs while still maintaining high performance.

This work follows a recent discovery by the research group that there is a competition between the SET and RESET process in cation-based RRAM, which causes failure of reset operation in the RRAM device. The researchers found that the active metal which forms a conductive filament can diffuse into the Pt electrode under the action of an electric field, and form an additional active metal source in Pt electrode, which caused the failure of reset operation. Using graphene as an ion barrier is a solution to this problem.

A couple of months ago, we reported that Israel-based RRAM developer Weebit Nano partnered with France-based research institute Leti, to co-develop advanced RRAM devices based on silicon oxide.

Weebit Nano now announced that its SiOx ReRAM memory technology has been successfully transferred from Rice University’s facilities to Leti’s pre-industrialisation facility in Grenoble, France. Leti's initial experiments confirm that Weebit’s unique nano-porous SiOx process is reproducible.

Australia-based RRAM developer 4DS Memory announced that it developed a working 40nm RRAM memory cells. This was achieved in collaboration with HGST, a subsidiary of Western Digital.

The 4DS memory cell is constructed using an advanced perovskite material, which has the same crystal structure as the inorganic compound calcium titanium oxide. The cells have no filaments and are so easier to scale compared to filamentary RRAM.

Israel-based RRAM developer Weebit Nano announced that it partnered with France-based research institute Leti. Leti and Weebit Nano will work on advanced RRAM devices based on silicon oxide.

As part of that agreement, Weebit will gain access to the advanced facilities of Leti, including an 8,500 square meters semiconductor cleanroom area.

Researchers developed a new high-performance bilayer self-selective RRAM device by using HfO2 as a memory swtching layer and mixed ionic and electron conductor as selective layer. The researchers say that this device exhibits high nonlinearity and ultra-low half-select leakage.

This new design may be a way to integrate individual selector devices with memory cell separately in a vertical RRAM device. The researchers successfully demonstrated a four layer vertical crossbar array - with high uniformity, ultra-low leakage, sub-nA operation, self-compliance, and excellent read/write disturbance immunity.

Strategic Elements reports that the alternative fabrication method it started investigating a few weeks ago has succeeded in creating a layer of nanocube ink over five times thinner than achieved previously with increased performance.

The surface roughness and uniformity of the nanocube layer was also significantly enhanced. The new method was developed and optimized at the University of New South Wales.

Crossbar announced a strategic partnership with Semiconductor Manufacturing International Corporation (SMIC) - China's largest semiconductor foundry. The two companies agreed to co-develop and produce RRAM technologies.

Crossbar says that as the company enters the licensing phase, it is honored to collaborate with SMIC - which is a major stepping stone towards its RRAM technology commercialization.